A high-speed low-power D flip-flop

Author

Chandrasekaran, Rajasekaran ; Lian, Yong ; Rana, Ram Singh

Author_Institution

Inst. of Microelectron., Singapore

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

82

Lastpage

85

Abstract

This paper proposes a new D flip-flop configuration based on differential cascode voltage switch with pass-gate logic. The circuit is able to reduce the transition time from the input to output. The flip-flop was implemented in 0.18 mum CMOS technology. The flip-flop was simulated using HSPICE to assess the performance and was further evaluated by measurements on a test chip. The maximum operating frequency of the flip-flop is 5 GHz according to simulation. The test chip operates correctly at 3 GHz. This performance makes it one of the fastest flip-flops with a rail-to-rail input and voltage swing

Keywords

CMOS logic circuits; flip-flops; high-speed integrated circuits; low-power electronics; 0.18 micron; 3 GHz; 5 GHz; CMOS technology; HSPICE; circuit simulation; differential cascode voltage switch; high-speed D flip-flop; low-power D flip-flop; pass-gate logic; rail-to-rail input; voltage swing; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit testing; Flip-flops; Frequency; Rail to rail inputs; Semiconductor device measurement; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611273

Filename

1611273