Title :
A Chopper-Stabilized Lateral-BJT-Input Interface in 0.6μm CMOS for Capacitive Accelerometers
Author :
Zhao, Dongning ; Zaman, M. Faisal ; Ayazi, Farrokh
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA
Abstract :
We present a prototype lateral-PNP (LPNP) BJT interface IC for an SOI capacitive accelerometer with a measured resolution of 6.3mug/VHz and an output noise floor of -118dBVradicHz for a gain of 204mV/g at extremely low frequencies. The resolution is improved by further reducing the low-frequency Vf noise and offset of the LPNP input interface using a chopper stabilization technique. The interface is designed and fabricated in a 3V 0.6mum CMOS process and interfaced with the accelerometer device with wire-bonds, where the accelerometer is fabricated on an SOI substrate using a simple process that yields high sensitivity in a small die size. The power consumption of the IC is 3.75mW with external clocking.
Keywords :
CMOS integrated circuits; accelerometers; bipolar transistors; capacitive sensors; silicon-on-insulator; CMOS integrated circuit; SOI capacitive accelerometer; bipolar transistors; chopper stabilization; external clocking; integrated circuit yield; lateral-BJT-input interface; power 3.75 mW; power consumption; size 0.6 mum; voltage 3 V; Accelerometers; CMOS process; Choppers; Frequency measurement; Gain measurement; Integrated circuit noise; Low-frequency noise; Noise measurement; Noise reduction; Prototypes;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523318
