VLSI architecture of EBCOT tier-2 encoder for JPEG2000

Author

Liu, Leibo ; Chen, Ning ; Zhang, Li ; Wang, Zhihua

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

173

Lastpage

176

Abstract

This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18mum 1P6M CMOS technology

Keywords

CMOS integrated circuits; VLSI; block codes; digital signal processing chips; image coding; integrated circuit design; rate distortion theory; 0.18 micron; EBCOT tier-2 encoder; JPEG2000 codec; RD slope method; SMIC 1P6M CMOS technology; VLSI architecture; compression bit-rate; embedded block coding with optimized truncation; on-chip bit-stream buffering; rate-distortion slope method; three-code-block size; Arithmetic; Bandwidth; Block codes; CMOS technology; Discrete wavelet transforms; Image coding; Rate-distortion; Tiles; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611290

Filename

1611290