A high performance Rad hard 2-3 GHz integer N CMOS phase lock loop

Author

Lyons, Gene ; Wu, Gary ; Mellissinos, Tony ; Cable, Jim

Author_Institution

Peregrine Semicond. Corp., San Diego, CA, USA

fYear

1999

fDate

1999

Firstpage

41

Lastpage

45

Abstract

We report here on the performance of a 2-3 GHz Phase Lock Loop (PLL) designed specifically for commercial space applications requiring low power dissipation, very good phase noise, good temperature stability, excellent SEE tolerance, and little degradation over a 100 kRad(Si) total dose exposure. The device is built in a 0.5 μm fully depleted ultra thin silicon on sapphire technology (UTSi). Product level radiation data is presented showing performance as a function of total dose. Following gamma exposures to 100 kRad(Si), the device shows an integrated phase noise of less than 0.8 degree for 2.18 GHz operation for frequency step sizes of 1 MHz. This is a performance level exceeding all known integrated PLL´s currently in the commercial marketplace

Keywords

CMOS integrated circuits; UHF integrated circuits; elemental semiconductors; gamma-ray effects; integrated circuit noise; phase locked loops; radiation hardening (electronics); silicon; silicon-on-insulator; space vehicle electronics; thermal stability; 0.5 mum; 100 krad; 2 to 3 GHz; PLL; SEE tolerance; Si-Al₂O₃; degradation; fully depleted ultra thin silicon on sapphire technology; gamma exposure; high performance Rad hard integer N CMOS phase lock loop; integrated phase noise; low power dissipation; phase noise; product level radiation data; space applications; temperature stability; total dose; Manufacturing processes; Performance evaluation; Phase locked loops; Phase noise; Semiconductor device manufacture; Semiconductor films; Silicon; Single event upset; Space technology; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation Effects Data Workshop, 1999

Conference_Location

Norfolk, VA

Print_ISBN

0-7803-5660-8

Type

conf

DOI

10.1109/REDW.1999.816055

Filename

816055