A Solid State Neuron for the Realisation of Highly Scaleable Third Generation Neural Networks

The paper describes a novel silicon synapse based on a two stage charge-coupled device with the weighting functionality integrated into the first stage by means of a floating gate. A spike input to the second gate allows the charge under the first gate to drift onto the floating diffusion output stage to produce a voltage spike. Parallel defined synapses are assigned to the drain of the input MOSFET of the current mirror which serves as the point neuron. This configuration provides a summing function and allows the transfer of the spikes. The neuron and its associated solid state synapses comprise a highly compact and scaleable neural cell which operates at very low power levels because of its charge coupled operation