A 12-bit 250-MHz current-steering DAC

In this paper, we propose a 12-bit 250-MHz current-steering digital-to-analog converter (DAC). In order to obtain better performances of INL, glitch energy, and monotonicity, we adopt the segmented architecture to design the DAC. In the segmented architecture, 7-MSBs are decoded into 127 equally weighted current sources, and 5-LSBs are corresponding to binary-weighted current sources. Based on the TSMC 0.35mum 2p4m CMOS technology, we use HSPICE to simulate the proposed DAC. The simulation results show that the proposed DAC has the following characteristics: INL= plusmn0.5LSB, DNL = plusmn0.25LSB, and settling time is less than 4ns. Under the condition of 250MHz update rate (f_CLK) and 3 MHz and 120 MHz output frequencies, the proposed converter´s spurious free dynamic ranges (SFDRs) are larger than 74 dB and 62 dB, respectively. The power consumption is 66.5 mW at the maximum conversion rate