DocumentCode
3468860
Title
Yield Modeling of Arbitrary Defect Outline
Author
Wang, Junping ; Hao, Yue
Author_Institution
Sch. of Commun. Eng., Xidian Univ., Xi´´an
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
1183
Lastpage
1185
Abstract
In integrated circuits(IC), the defects associated with photolithography are assumed to be the shape of circular discs in order to perform the estimation of yield and fault analysis. However, real defects exhibit a great variety of shapes. Based on the real outlines of the defects and the mathematical morphology, a novel yield model is presented and the critical area model is provided correspondingly. Since they avoid changing the defects into the shape of circular discs, the models predict the yield caused by the defects more accurately than the circular discs model does. Experimental results showing the model´s performance are presented. It is significant that the yield is accurately estimated using the proposed model
Keywords
fault simulation; integrated circuit modelling; integrated circuit yield; photolithography; arbitrary defect outline; fault analysis; integrated circuits model; mathematical morphology; photolithography; yield modeling; Integrated circuit modeling; Integrated circuit yield; Manufacturing; Mathematical model; Morphology; Predictive models; Production; Semiconductor device modeling; Shape measurement; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306070
Filename
4098361
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