Title :
Parity sensitive comparators
Author :
Fabregat, Germán ; Martí, José V. ; León, Germán
Author_Institution :
Dept. de Inf., Jaume I Univ., Castellon, Spain
Abstract :
Parity sensitive comparators are a new type of comparators designed to take advantage of the parity information present in most buses. Instead of simply comparing the signals carried by the buses, parity information is used to select the probably correct output in case of mismatch, thus avoiding an important percentage of errors to stop system functioning. These devices verify parity for each pair of compared groups and discard erroneous data when comparing, propagating the probably correct data and signaling the fact with a “recoverable error” output signal. Benefits of parity sensitive comparators are analyzed by means of a deep probabilistic study of the “parity bit per data byte” case that shows how they are able to recover more than the 97% of errors signaled by classical comparators. The output information of the comparators is also described, as well as its uses according to the level of reliability required
Keywords :
comparators (circuits); fault tolerant computing; system buses; buses; deep probabilistic study; discard erroneous data; error recovery; mismatch; output information; parity bit per data byte; parity information; parity sensitive comparators; probably correct output selection; recoverable error output signal; reliability; Concrete; Error correction; Error correction codes; Performance evaluation; Proposals; Protection; Signal analysis; Signal processing; System buses; Voting;
Conference_Titel :
Dependable Computing, 1999. Proceedings. 1999 Pacific Rim International Symposium on
Print_ISBN :
0-7695-0371-3
DOI :
10.1109/PRDC.1999.816212