A low-voltage low-power CMOS sample-and-hold circuit

A low power supply sample-and-hold circuit for a pipelined analog-to-digital converter is described. Several approaches have been used to reduce the power consumption, including a gain-compensated structure and a simple optimum allocation of settling time parameter. To reduce the nonlinear error of the sampling switch, a signal dependent clock bootstrapping system is used. Simulation results demonstrate that the S/H circuit consumes only 2.3 mWat 1.8v supply with an accuracy of 10bit and a sampling rate of 50M