DocumentCode :
3469381
Title :
A scheduling approach for packet-switched on-chip networks
Author :
Salah, Y. ; Zeghid, M. ; Bennour, I.E. ; Tourki, Rached
Author_Institution :
Lab. of Electron. & Microelectron., Univ. of Monastir, Monastir, Tunisia
fYear :
2011
fDate :
3-5 March 2011
Firstpage :
1
Lastpage :
8
Abstract :
Performance constraints imposed on the on-Chip System (SoC) design require efficiency and predictability of inter-core communication part in system. This implies the Quality-of-Service (QoS) requirement assurance for the communication. The current work presents a novel approach that borrows three Real-Time Operating System (RTOS) scheduling algorithms and adapts them to Networks-on-Chip (NoCs). This technique is designed specifically for multimedia and safety-critical real-time applications to reduce contention problem in packet-switched networks and provides QoS guarantees in terms of throughput and end-to-end latency. An HDL implementation of a NoC architecture has been simulated to prove our concept.
Keywords :
hardware description languages; network-on-chip; operating systems (computers); packet switching; quality of service; scheduling; contention problem; hardware description languages; inter-core communication; networks-on-; packet-switched networks; packet-switched on-chip networks; performance constraints; quality-of-service; real-time operating system scheduling; Hardware design languages; Scheduling; Switches; Network-on-Chip; Quality-of-Service; design; implementation; packet scheduling; performance; router;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computing and Control Applications (CCCA), 2011 International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4244-9795-9
Type :
conf
DOI :
10.1109/CCCA.2011.6031503
Filename :
6031503
Link To Document :
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