DocumentCode
3469475
Title
A new test data compression/decompression scheme to reduce SOC test time
Author
Jieyi, Long ; Jianhua, Feng ; Zhu Iida ; Wenhua, Xu ; Xinan, Wang
Author_Institution
Dept. of Microelectron., Peking Univ., Beijing, China
Volume
2
fYear
2005
fDate
24-27 Oct. 2005
Firstpage
685
Lastpage
688
Abstract
A new test data compression/decompression scheme based on Huffman coding is proposed in this paper for reducing the amount of test data transferring between ATE and CUT so as to shorten the test time of IP core-based SOC designs. The compression algorithm accomplishes in two steps - first, don´t cared bits in the original test data are specified by a dedicated algorithm; then a Huffman-coding-like procedure would be applied to the fully-assigned test data. Instead of splitting test data into fix-length blocks, as it is in traditional Huffman coding, in our approach, the test data are partitioned into blocks of two lengths, namely shortWord and longWord. Both theoretical analysis and experimental results show that our scheme results in high compression ratio as well as small decompression overhead.
Keywords
Huffman codes; automatic test equipment; data compression; integrated circuit design; logic testing; system-on-chip; Huffman coding; IP core-based SOC designs; SOC test time reduction; automatic test equipment; circuit under test; fix-length blocks; test data compression; test data decompression; Circuit testing; Compression algorithms; Decoding; Greedy algorithms; Hardware; Huffman coding; Integrated circuit testing; Microelectronics; Partitioning algorithms; Test data compression; SOC; decompression overhead; don´t cared bits specification; test compression; test data partition;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611413
Filename
1611413
Link To Document