A low-cost BIST scheme for ADC testing

Author

Yong-sheng, Wang ; Jin-xiang, Wang ; Feng-chang, Lai ; Yi-zheng, Ye

Author_Institution

Microelectron. Center, Harbin Inst. of Technol.

Volume

2

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

694

Lastpage

698

Abstract

A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated

Keywords

analogue-digital conversion; built-in self test; delta-sigma modulation; integrated circuit testing; ADC testing; BIST scheme; built-in self-test; digital delta-sigma noise shaping; linear histogram; linear waveform generator; on-chip precise analog stimulus; parallel time decomposition; triangular waveform generator; Automatic testing; Built-in self-test; Circuit testing; Digital signal processing; Digital signal processing chips; Hardware; Histograms; Microelectronics; Random access memory; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611416

Filename

1611416