DocumentCode :
3469595
Title :
Study on analyzing and modeling of delay activity for digital circuit
Author :
Ma, Minjie ; Li, Zheying ; Jin, Guangyu
Author_Institution :
Sch. of Electron. & Inf. Eng., Beijing JiaoTong Univ., China
Volume :
2
fYear :
2005
fDate :
24-27 Oct. 2005
Firstpage :
714
Lastpage :
718
Abstract :
A novel modeling method of longest path detecting for signal transmission and delay time computing of logic circuit is proposed in this paper. The method is based on graph theory so that it is quite simple. This paper introduces matrixes based on the circuit´s neighborhood graph, which is a labeled and directed graph G, 2-tuple G (V, E). The gate-level circuit is first transformed into a directed acyclic graph in which the gates appear as edges with certain option value and the signals correspond to the nodes marked with number. The neighborhood graph is then mapped onto a conjunction matrix. The novel method could also give the formulas of calculating the delay time as well as detecting the longest path of delay.
Keywords :
digital circuits; directed graphs; logic circuits; logic testing; matrix algebra; conjunction matrix; delay activity; delay time computing; digital circuit; directed acyclic graph; gate-level circuit; graph theory; labeled graph; logic circuit; longest path detecting; neighborhood graph; signal transmission; Circuit simulation; Delay effects; Delay estimation; Digital circuits; Frequency; Graph theory; Logic circuits; Process design; Signal detection; Transmission line matrix methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
Type :
conf
DOI :
10.1109/ICASIC.2005.1611420
Filename :
1611420
Link To Document :
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