DocumentCode :
3469609
Title :
A novel method for the construction of self-dual circuits
Author :
Wei, Wang ; Jianhui, Jiang
Author_Institution :
Dept. of Comput. Sci. & Technol., Tongji Univ., Shanghai, China
Volume :
2
fYear :
2005
fDate :
24-27 Oct. 2005
Firstpage :
661
Lastpage :
665
Abstract :
This paper presents a more area-effective method to construct self-dual circuits. The experimental results based on ISCAS85 benchmark circuits show that the proposed method can considerably decrease hardware complexity on average. If the circuit has few primary input and primary output lines, the proposed method is superior when the circuit scale becomes larger.
Keywords :
combinational circuits; fault tolerance; logic testing; sequential circuits; fault tolerance; hardware complexity; online test; self-dual circuit construction; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Error correction; Fault tolerance; Hardware; Logic testing; Redundancy; Sequential circuits; fault tolerance; hardware complexity; online test; self-dual circuit;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
Type :
conf
DOI :
10.1109/ICASIC.2005.1611421
Filename :
1611421
Link To Document :
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