Title :
A novel method for the construction of self-dual circuits
Author :
Wei, Wang ; Jianhui, Jiang
Author_Institution :
Dept. of Comput. Sci. & Technol., Tongji Univ., Shanghai, China
Abstract :
This paper presents a more area-effective method to construct self-dual circuits. The experimental results based on ISCAS85 benchmark circuits show that the proposed method can considerably decrease hardware complexity on average. If the circuit has few primary input and primary output lines, the proposed method is superior when the circuit scale becomes larger.
Keywords :
combinational circuits; fault tolerance; logic testing; sequential circuits; fault tolerance; hardware complexity; online test; self-dual circuit construction; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Error correction; Fault tolerance; Hardware; Logic testing; Redundancy; Sequential circuits; fault tolerance; hardware complexity; online test; self-dual circuit;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611421