Addressable test-chip compiler for test chip design automation and transistor/yield characterization

Addressable arrays have been used in the semiconductor industry for process characterization. Compared with traditional test structures with probing pads, addressable arrays require much less pads, therefore save significantly on mask/wafer areas and testing time (due to less prober movement). However, because current from device under test (DUT) must be measured through addressable circuitry in this approach, it remains a big challenge to adopt this approach for full transistor characterization including leakage current measurement. Here we report, for the first time, an addressable array test chip that is capable of full transistor characterization including measuring transistor off current. The design of the test chips and silicon verification of its accuracy is discussed. In addition, various DUT´s of different sizes and functions can be automatically integrated into addressable arrays through an “Addressable Test-chip Compiler” approach.