An optimized adder accumulator for high speed MACs

A novel architecture of adder with accumulation register here called adder accumulator (AAC) is presented. When used for the implementation of a MAC, it drastically reduces the delay of the final adder portion with a very small extra area consumption. The novel architecture merges the adder block and the accumulator register present in the MAC operator furnishing the possibility to use two separate n/2 bit adders instead of the n bit adder generally employed to accumulate the n bit MAC result