Analysis of Fringing-Electric-Field-Related Capacitance Behavior of Narrow-Channel FD SOI NMOS Devices Using 3D Simulation

Author

Chen, C.C. ; Lin, O.G. ; Kuo, J.B.

Author_Institution

Dept. Elec. Eng., National Taiwan Univ., Taipei

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1376

Lastpage

1379

Abstract

This paper reports the fringing-electric-field-related capacitance behavior of narrow-channel FD SOI NMOS devices using 3D simulation. Based on the results, with a channel width of 0.05 mum, the inner sidewall oxide capacitance (C_FIS) due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V_G=0.3V and V_D=1V, is the second largest contributor to the gate-source capacitance (C_GS)-35%. Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 mum, C_FIS cannot be overlooked for modeling gate-source/drain capacitance (C_GS/C _GD)

Keywords

CMOS integrated circuits; MOS integrated circuits; VLSI; integrated circuit modelling; silicon-on-insulator; 0.05 micron; 0.3 V; 1 V; 3D simulation; FD SOI NMOS devices; fringing-electric-field-related capacitance behavior analysis; gate-source capacitance; gate-source/drain capacitance modeling; inner sidewall oxide capacitance; nanometer CMOS devices; Analytical models; CMOS technology; Capacitance; Doping; MOS devices; Mesh generation; Nanoscale devices; Semiconductor device modeling; Thin film devices; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306188

Filename

4098414