Optimal lot sizing for 3DIC products in backend manufacturing

Cycle time reduction is a critical task in semiconductor industries to keep market competitive advantage. Small lot size manufacturing (SLM) is one of the methods to achieve this goal efficiently. Motivated by a new technology of three dimensional integrated circuit (3DIC) and the characteristics of equipments and process flow, we discuss a different lot sizing manufacturing strategy to achieve cycle time reduction in a backend manufacturing. There is rare literature to investigate the overall benefits and impacts of SLM applied for 3DIC manufacturing. This study fills this gap and provides a mathematical model to evaluate the tradeoff among cycle time performance, tool productivity and carrier loading with the objective being to minimize overall costs. A practical case conducted from a semiconductor manufacturer in Taiwan is illustrated in this study. Furthermore, to keep tool productivity, the effects and benefits of lot grouping in batch process tool are discussed. The model proposed helps managers to determine the optimal lot sizing and ensure that it is worthwhile to adopt SLM for 3DIC products in the backend manufacturing.