An embedded DRAM module using a dual sense amplifier architecture in a logic process

Author

Hashimoto, M. ; Abe, K. ; Seshadri, A.

Author_Institution

Texas Instrum. Japan Inc., Ibaraki, Japan

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

64

Lastpage

65

Abstract

A dual sense amplifier array architecture (DSSA) amenable to a logic-process-compatible 1T DRAM eliminates the penalty that can be imposed by any two-bank-architecture-based DRAM. A 32k/spl times/16 eDRAM test chip is used to verify the architecture. The chip is implemented in a 0.5 /spl mu/m single-poly, triple-metal CMOS process. The DRAM array cell capacitance and bitline parasitic capacitance are 23 fF and 550 fF, respectively. The DRAM cell is 33 /spl mu/m/sup 2/ (7.38/spl times/4.5 /spl mu/m/sup 2/).

Keywords

CMOS memory circuits; DRAM chips; capacitance; memory architecture; 0.5 micron; 23 fF; 512 kbit to 1 Tbit; 550 fF; bitline parasitic capacitance; cell capacitance; dual sense amplifier array architecture; dynamic RAM; embedded DRAM module; logic-process-compatible DRAM; single-poly triple-metal CMOS process; Circuits; Decision support systems; Geometry; Instruments; Logic arrays; Random access memory; Read-write memory; Signal generators; Subthreshold current; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585262

Filename

585262