Title :
A 1.2 V to 3.3 V wide-voltage-range DRAM with 0.8 V array operation
Author :
Tsukude, M. ; Kuge, S. ; Fujino, T. ; Arimoto, K.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
DRAM arrays operating with power supply below 1 V, with stable sensing and high speed are required for multi-media systems. Reduction of data-retention current is also important. The authors present two data-retention current reduction techniques: charge-transfer pre-sensing scheme (CTPS) with 1/2Vcc bit-line precharge; and non-reset row block control (NRBC). An experimental 32 Mb DRAM using these techniques is fabricated in a 0.25 /spl mu/m triple-well CMOS technology.
Keywords :
CMOS memory circuits; DRAM chips; 0.25 micron; 0.8 V; 1.2 to 3.3 V; 32 Mbit; DRAM arrays; bit-line precharge; charge-transfer pre-sensing scheme; data-retention current reduction; dynamic RAM; nonreset row block control; triple-well CMOS technology; wide-voltage-range DRAM; Charge transfer; Circuits; Laboratories; Logic; Multimedia systems; Power supplies; Random access memory; Threshold voltage; Timing; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585263
