Title :
Area optimization in deep sub-micron VLSI design
Author :
Dong-hui, Wang ; Qian, Yu ; Yan, Liu
Author_Institution :
Inst. of Acoust., Chinese Acad. of Sci., Beijing
Abstract :
Area is an important factor in deep sub-micron VLSI design. In order to save die size during back-end design for our DSP microprocessor - SuperV, double metal power rings were designed, and some standard cells were also put under the horizontal power straps. In this way, more than 12% die size saved. Other optimization methods were also introduced to save area during placement and routing. Finally, the core area is shrank to 4mm times 4mm, and the chip´s area is decreased to 5mm times 5mm including the bonding pads
Keywords :
VLSI; circuit optimisation; digital signal processing chips; integrated circuit design; logic design; DSP microprocessor; SMIC IP6M CMOS technology; SuperV processor; area optimization; back-end design; bonding pads; deep sub-micron VLSI design; double metal power rings; horizontal power straps; Clocks; Costs; Design optimization; Digital signal processing; Microprocessors; Packaging; Production; Timing; VLIW; Very large scale integration; Area; Power Ring; Timing; VLSI;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611448
