A 16 b 100 k sample/s 2.7 V 25 mW ADC/DSP/DAC-based analog signal processor in 0.8 /spl mu/m CMOS

Author

Dedic, I.J. ; Amos, N.C. ; King, M.J. ; Schofield, W.G. ; Kemp, A.K.

Author_Institution

European Mixed-Signal ASIC Design Centre, Fujitsu Microelectron. Ltd., Berks., UK

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

96

Lastpage

97

Abstract

The 0.8/spl mu/m CMOS signal processor described combines a low-noise analog front-end and reference, 16b ADC/DAC, and 16b DSP optimized for filter applications. With 25mW typical power consumption at 100kSample/s (3mW for ADC/DAC) it can be programmed for high-order analog filtering and other signal processing functions with 80dB typical SNR.

Keywords

CMOS integrated circuits; active filters; analogue processing circuits; analogue-digital conversion; digital signal processing chips; digital-analogue conversion; integrated circuit noise; mixed analogue-digital integrated circuits; 16 bit; 2.7 V; 25 mW; 3 mW; ADC/DSP/DAC-based analog signal processor; CMOS; SNR; filter applications; high-order analog filtering; low-noise analog front-end; power consumption; signal processing functions; CMOS process; Circuits; Clocks; Digital signal processing; Energy consumption; Filtering; Filters; Read-write memory; Signal processing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585278

Filename

585278