Title :
A universal hierarchical FPGA partitioning algorithm
Author :
Chen, Yuanfeng ; Tang, Pushan ; Lai, Jinmei ; Tong, Jiarong
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai
Abstract :
HFPGA (hierarchical FPGA) is a common FPGA architecture in industry. The paper presents an improved partition algorithm based on previous hierarchical FPGA partitioning works. The algorithm combines the simulated annealing algorithm with ratio-cut method to decide the level of the multi-level multi-way partitioning. We consider the number of cut lines while partitioning CLBs into cluster, so as to achieve a better partitioning result and improve the usage rate in HFPGA, then optimize the FPGA performance
Keywords :
field programmable gate arrays; logic partitioning; simulated annealing; FPGA architecture; hierarchical FPGA partitioning algorithm; multilevel multiway partitioning; ratio-cut method; simulated annealing algorithm; Application specific integrated circuits; Circuit simulation; Clustering algorithms; Data structures; Field programmable gate arrays; Laboratories; Microelectronics; Partitioning algorithms; Routing; Simulated annealing; HFPGA; Hierarchical FPGA; partition;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611451
