A datapath routing algorithm using bit regularity extraction

As the technology migrates into ultra deep sub-micron era, the timing characteristics of datapath circuits are greatly affected by their wire pattern and length. To ensure data signals arriving simultaneity, nets from same bus should better be equal in length or pattern alike. In consideration of above, we propose a detail router especially designed for datapath circuit. Datapaths are usually composed of regular bits which are replicated for certain times. Exploiting this regularity, bits are first grouped by the type of nets and predefined obstacles they contain. Then constructed force directed (CFD) Steiner Tree routing is performed on exactly one representative bit selected from each group. Next, the route result of representative bit is propagated to all other bits in its group. Experiments were done on industrial datapath instances. Results show a short run-time and the route results in regular and predictable layout