Si/SiGe CMOS: can it extend the lifetime of Si?

Author

Ismail, K.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

116

Lastpage

117

Abstract

Modifications to the intrinsic and extrinsic aspects of state-of-the art Si CMOS technology are presented. Measured circuit performance of n-type Si/SiGe FETs proves that a factor of 10 in power-delay is possible. Microwave performance of both n- and p-type FETs based on strained Si/SiGe also corroborate the above result. Simulated circuit performance of 0.1 /spl mu/m Si/SiGe CMOS based on the above experimental results is presented and compared to bulk Si CMOS and SOI. Also a process for Schottky source/drain self-aligned T-gate FET is demonstrated.

Keywords

CMOS integrated circuits; Ge-Si alloys; Schottky gate field effect transistors; integrated circuit technology; microwave field effect transistors; silicon; 0.1 micron; Schottky source/drain self-aligned T-gate FET; Si-SiGe; Si/SiGe CMOS technology; circuit simulation; microwave performance; n-type FET; p-type FET; power-delay product; CMOS process; CMOS technology; Charge carrier processes; Circuit simulation; Delay; FETs; Germanium silicon alloys; MOS devices; Ohmic contacts; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585282

Filename

585282