A technique to exploit memory locality for fast instruction set simulation

To verify software and system functionality during the design process of complex SoCs, designers routinely use instruction set simulators (ISSs) as high level processor models. Typically, an ISS needs to simulate billions of target instructions to verify a single task of the system in design, which is a very time-consuming process. Therefore, the simulation speed of ISSs has become one important concern of SoC designers. In this paper, we present a new technique to improve the speed of ISSs. Specifically, we focus on the translation of memory addresses between the target memory space and the host memory space. Such translation is performed by a hash table in many ISS implementations. To accelerate the translation, we introduce a software cache called translation buffer (TB) to cache the hashing results for quick future access. With properly chosen TB sizes, our implementation effectively exploits the abundant locality inherent in the memory footprints of real-world application programs and greatly reduces the overall address translation overhead. We integrated the technique into three popular ISSs and achieved a 15-32% improvement in simulation speed.