Title :
Transition traversal coverage estimation for symbolic model checking
Author :
Xu, Xingwen ; Kimura, Shinji ; Horikawa, Kazunari ; Tsuchiya, Takehiko
Author_Institution :
Graduate Sch. of IPS, Waseda Univ., Japan
Abstract :
Model checking can exhaustively verify a set of specified properties on a given implementation. However, it is very hard to determine whether sufficient properties have been specified or not. In this paper, we propose a transition traversal coverage method for a subset of CTL to evaluate the completeness of properties. With this method, we can detect the transitions which are not verified by any property. It is more comprehensive and accurate than state-based coverage metric. We avoid generating the perturbed implementation by directly traversing transitions based on the semantics of CTL formulas. Experimental results show that the proposed method can discover subtle coverage holes with low computation cost.
Keywords :
finite state machines; formal verification; logic testing; CTL formulas; symbolic model checking; transition traversal coverage estimation; Automata; Computational efficiency; Computer bugs; Formal verification; Large scale integration; Logic; Productivity; Sequential circuits; Time to market;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611460