A 170 mW 10 b 50 Msample/s CMOS ADC in 1 mm/sup 2/

This 10 b AD-converter at a sample rate of 5O MSample/s, embedded in 50mm/sup 2/ of digital circuitry, shows 8.7 effective bits. A straight flash-architecture would need 1023 accurate fast comparators. With a 2 V input range, a comparator offset voltage of no more than 1 mV can be tolerated. Taking into account that the 1 mV is a 3-6 sigma value, leads to a large chip. If, however, the signals to the comparator are amplified before the critical decision, simple small comparators would suffice. To cope with the dynamic offset caused by the clocking and latch action of the comparator itself, the architecture must tolerate comparator offsets of up to 60-80 mV. Hence, a gain of at least 30 is necessary. A single amplifier however, could not handle this, as the input range of 2 V would be amplified to 60 V. The approach here is to use a distributed amplifier.