A 12 b 128 MSample/s ADC with 0.05 LSB DNL

This analog-to-digital converter uses integrated dither, dynamic element matching, and output data scrambling to achieve SFDR of 85dB and DNL below 0.05LSB at l28MSample/s. This compares to about 0.5LSB DNL for slower 12b converters. The basic two-step flash architecture is shown. The /spl plusmn/0.25V input is amplified to /spl plusmn/1V and held in the track-and-hold circuit when the input clock rises. The 32 comparators in ADC1 produce an approximation that switches the 32 matched current sources in the main DAC. The residue is formed and amplified in the summer to /spl plusmn/0.5V and is converted by ADC2, an 8b folding-and-interpolating flash ADC. To allow low clock rates, there is no analog pipelining, and all analog settling from the track-to-hold transition to latching the result in ADC2 takes only 4.4ns. The ADC1 and ADC2 results added together form the 12b output. The total signal-to-data-output delay is slightly more than two cycles due to digital pipelining.