FSM decomposition for power gating design automation in sequential circuits

Power gating is one of the most effective techniques for low power design because it reduces both dynamic and static power simultaneously. This paper proposes a circuit architecture to implement power gating in sequential circuits based on finite state machine (FSM) decomposition, which is implemented by partition the state transition graph (STG). The FSM is partitioned into two or more sub-machines, only one of which is active most of the time, and the power supply of other sub-machines can be cut off to save energy. Since adjustment of supply voltage may not finish instantly, the voltage of the submachine that will be activated need to be raised ahead of time, which makes the problem complicated. We propose a simulated annealing algorithm to perform the decomposition without timing penalty. Experimental results have shown the effectiveness of our approach, and it is expected that power gating will show superior power saving to clock gating due to the increasing significance of static power.