Title :
A 622 Mb/s 32/spl times/8 scalable ATM switch chip set with on-chip searchable address queue
Author :
Notani, H. ; Kondoh, H. ; Saito, H. ; Ishiwaki, M. ; Yoshimura, T. ; Sasaki, Y. ; Nishio, S. ; Iwabu, A. ; Kohama, S. ; Kitao, M. ; Takashima, M. ; Oshima, K. ; Matsuda, Y.
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A 0.5 /spl mu/m CMOS 622Mb/s 32/spl times/8 shared-buffer ATM switch chip set consists ofa buffer LSI and a control LSI. It has a 768-cell on-chip buffer controlled by a searchable address queue running at 400 MHz with a double-edge triggered hand-shake circuit. The switch realizes 5 Gb/s total throughput with 8-level delay and 4-level cell-loss priorities for multimedia communications. A funnel structure enables a scalable switch size. 32 bit/frame synchronizers are integrated for all input channels.
Keywords :
CMOS digital integrated circuits; asynchronous transfer mode; buffer storage; multimedia communication; shared memory systems; switching circuits; telecommunication congestion control; 0.5 mum; 32 bit/frame synchronizers; 4-level cell-loss priorities; 400 MHz; 622 Mbit/s; 8-level delay; CMOS shared-buffer ATM switch chip set; buffer LSI; control LSI; double-edge triggered hand-shake circuit; funnel structure enables; multimedia communications; on-chip searchable address queue; scalable switch size; total throughput; Asynchronous transfer mode; Clocks; Communication switching; Communication system control; Delay; Large scale integration; Logic; Streaming media; Switches; Synchronization;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585310
