• DocumentCode
    3470501
  • Title

    Domain coverage metric for validation

  • Author

    Chun, Luo ; Gugang, Gao ; Jun, Yang

  • Author_Institution
    National ASIC Syst., Southeast Univ., Nan Jing
  • Volume
    2
  • fYear
    2005
  • fDate
    24-0 Oct. 2005
  • Firstpage
    957
  • Lastpage
    960
  • Abstract
    The importance of validation continues to grow with the increase of design size. How to measure the completeness and quality of validation approach? Existing coverage metrics are oversimplified and incapable to reveal design faults, so we proposed and developed an innovative coverage metric, domain coverage metric. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that points on or near the boundary are most sensitive to domain errors. The coverage tool have been implemented using Verilog procedural interface (VPI) and have been applied to validation of industrial system on chip (SoC) under design. Results show that the domain coverage can detect many design faults that statement and path coverage can not
  • Keywords
    fault diagnosis; hardware description languages; integrated circuit design; system-on-chip; Verilog procedural interface; design faults; domain coverage metric; geometrical analysis; industrial system on chip; innovative coverage metric; validation; Acceleration; Application specific integrated circuits; Circuit faults; Counting circuits; Design engineering; Emulation; Formal verification; Hardware; Systems engineering and theory; Testing; Coverage; Domain; Stimulus Generation; Validation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2005. ASICON 2005. 6th International Conference On
  • Conference_Location
    Shanghai
  • Print_ISBN
    0-7803-9210-8
  • Type

    conf

  • DOI
    10.1109/ICASIC.2005.1611467
  • Filename
    1611467