Title :
Design of a Low-Power 8 x 8-Bit Parallel Multiplier Using MOS Current Mode Logic Circuit
Author :
Lee, Youn Sang ; Kim, Jeong Beom
Author_Institution :
Dept. of Electron. Eng., Kangwon Nat. Univ., Chuncheon
Abstract :
This paper proposes an 8 times 8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8 times 8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with Samsung 0.35 mum standard CMOS process
Keywords :
CMOS logic circuits; current-mode logic; logic design; low-power electronics; multiplying circuits; 0.35 micron; 8 bit; HSPICE simulation; MCML full adders; MOS current mode logic circuit; parallel multiplier; standard CMOS process; Adders; Batteries; CMOS logic circuits; Capacitance; Energy consumption; Frequency; Inverters; Logic circuits; MOSFETs; Voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306271
