DocumentCode
3470705
Title
VLSI interconnect signal analysis using a projection framework method
Author
Suzuki, Goro
Author_Institution
Kitakyushu Univ., Fukuoka
Volume
2
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
1010
Lastpage
1016
Abstract
The Elmore base delay calculation method has long been in use, but this method cannot meet accuracy demands of current designs using deep sub-micron processes. On the other hand, SPICE can provide high accuracy, but it is very time consuming. Therefore, a novel, highly accurate and high-speed delay analysis method is proposed: MOR (model order reduction). We applied it in interconnect signal analysis to evaluate its performance
Keywords
SPICE; VLSI; delay estimation; integrated circuit interconnections; reduced order systems; Elmore base delay calculation; SPICE; VLSI interconnect signal analysis; model order reduction; projection framework; Bismuth; Circuit stability; Delay; Equations; Equivalent circuits; Integrated circuit interconnections; Signal analysis; Transfer functions; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611477
Filename
1611477
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