Title :
A 300 MHz CMOS microprocessor with multi-media technology
Author :
Choudhury, Mihir R. ; Miller, J.S.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
This 7.5M transistor CMOS microprocessor is architecturally equivalent to, and the next generation superset of, a previous microprocessor with dynamic execution (Colwell and Steek, 1995). It implements Intel MMX/sup TM/ Technology instructions to enhance performance of media and communication applications. It doubles the on-chip instruction and data caches of the previous generation processor to 16 kB each and implements a dedicated bus to access large off-chip second-level caches. This processor also implements renaming of data segment registers. These and other features result in projected performance of /spl sim/ 12.0 Specint95 for this 300 MHz processor and 3-12/spl times/ performance improvement for kernels of multimedia and communication applications (for example DSP, video and voice) over a scalar implementation. It is the highest performance Intel-Architecture compatible microprocessor.
Keywords :
CMOS digital integrated circuits; integrated circuit design; microprocessor chips; parallel architectures; pipeline processing; 0.35 mum; 300 MHz; CMOS microprocessor; DSP; Intel MMX Technology; Intel-Architecture compatible microprocessor; communication applications; data caches; data segment register renaming; dedicated bus; design methodology; large off-chip second-level caches; multi-media technology; on-chip instruction; performance improvement; video; voice; CMOS technology; Clocks; Decoding; Hardware; Logic; Microprocessors; Multimedia communication; Pipelines; Registers; Testing;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585320
