DocumentCode
3470746
Title
Implications of Memory-Efficiency on Sparse Matrix-Vector Multiplication
Author
Jain, Sonal ; Pottathuparambil, R. ; Sass, Ron
Author_Institution
Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
fYear
2011
fDate
19-21 July 2011
Firstpage
80
Lastpage
83
Abstract
Sparse Matrix Vector-Multiplication is an important operation for many iterative solvers. However, peak performance is limited by the fact that the commonly used algorithm alternates between compute-bound and memory-bound steps. This paper proposes a novel data structure and an FPGA-based hardware core that eliminates the limitations imposed by memory.
Keywords
data structures; field programmable gate arrays; iterative methods; matrix multiplication; sparse matrices; storage management chips; FPGA-based hardware core; commonly used algorithm; compute-bound step; data structure; iterative solver; memory efficiency; memory-bound step; peak performance; sparse matrix vector multiplication; Bandwidth; Data structures; Field programmable gate arrays; Hardware; Iterative methods; Sparse matrices; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Application Accelerators in High-Performance Computing (SAAHPC), 2011 Symposium on
Conference_Location
Knoxville, TN
Print_ISBN
978-1-4577-0635-6
Electronic_ISBN
978-0-7695-4448-9
Type
conf
DOI
10.1109/SAAHPC.2011.24
Filename
6031570
Link To Document