Gate delay estimation based on close-ended line model

Delay estimation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. Accurate estimation of gate delay closely depends on the model for the driving point admittance of a load interconnect tree. In this paper, a close-ended line model for transmission line tree reduction is proposed. The model can be applied to delay estimation of gate driving large transmission line tree. It features simple construction and high precision