Low-voltage double-sampled /spl Sigma//spl Delta/ converters

Author

Senderowicz, D. ; Nicollini, G. ; Pernici, S. ; Nagari, A. ; Confalonieri, P. ; Dallavalle, C.

Author_Institution

SynchroDesign Inc., Berkeley, CA, USA

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

210

Lastpage

211

Abstract

In theory, double-sampling in second-order /spl Sigma//spl Delta/ analog-to-digital converters (ADC) can enhance the signal-to-noise ratio (SNR) by 15 dB. In practice however, the SNR performance is usually severely degraded because of mismatches occurring in switched-capacitors (SC). This paper introduces a simple method to solve this problem. Regarding /spl Sigma//spl Delta/ digital-to-analog converters (DAC), in addition to double-sampling, the accompanying use of internal decimation helps to relax the bandwidth requirements of the opamps. Both circuitries are to be operational to supply voltages as low as 1.5 V by using clock bootstrapping. Chip implementation is in double-poly, 2-metal technology featuring 0.5 /spl mu/m minimum channel lengths.

Keywords

CMOS integrated circuits; digital-analogue conversion; integrated circuit noise; sigma-delta modulation; signal sampling; switched capacitor networks; 0.5 micron; 1.5 V; DAC; SC techniques; SNR performance; analog/digital converters; clock bootstrapping; digital/analog converters; double-poly 2-metal technology; double-sampled /spl Sigma//spl Delta/ converters; internal decimation; low-voltage converters; second-order type; signal/noise ratio; switched-capacitors; Clocks; Delta modulation; Dynamic range; Energy consumption; Filters; Frequency; Power supplies; Solid state circuits; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585336

Filename

585336