Low Power and High Speed Addition Strategies for VLSI

Very large scale integration (VLSI) adders are critically important in digital designs since they are utilized in ALUs, memory addressing, cryptography, and floating-point units. Since adders are often responsible for setting the minimum clock cycle time in a processor, they can be critical to any improvements seen at the VLSI level. However, fast logarithmic time adders can be impractical for a given VLSI implementation due to their prohibitive structures in terms of interconnect congestion, delay, and power. This paper discusses several adder designs and their analysis in the sub-micron and nanometer range and gives recommendations for choosing the best architectures for high-speed and low-power dissipation