Metal gate and high-k integration for advanced CMOS devices

Author

Guillaumot, B. ; Garros, Xavier ; Lime, Francois ; Oshima, K. ; Chroboczek, J.A. ; Masson, P. ; Truche, R. ; Papon, A.M. ; Martin, F. ; Damlencourt, J.F. ; Maitrejean, Sylvian ; Rivoire, Maurice ; Leroux, Camille ; Cristoloveanu, S. ; Ghibaudo, Gerard ; A

Author_Institution

STMicroelectronics, Crolles, France

fYear

2003

fDate

24-25 April 2003

Firstpage

56

Lastpage

60

Abstract

An advanced CMOS process has been proposed which include key features : 75 nm gate length, damascene metal gate, high-k dielectrics with 1.35 nm equivalent oxide thickness (EOT). Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface Low gate current and low subthreshold slope make it attractive for low stand by power application.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit metallisation; integrated circuit noise; 1.35 nm; 75 nm; C-V curve; CMOS down scaling; LF noise; Si-SiO₂; TEM; advanced CMOS devices; charge pumping; damascene metal gate; dielectric; equivalent oxide thickness; high quality; high temperature transport; high-k dielectrics; high-k integration; interface; low gate current; low stand by power application; low subthreshold slope; low temperature transport; n-MOSFET; p-MOSFET; split C-V; CMOS process; Capacitance-voltage characteristics; Charge pumps; High K dielectric materials; High-K gate dielectrics; Interface states; Low-frequency noise; MOSFET circuits; Microstrip; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma- and Process-Induced Damage, 2003 8th International Symposium

Print_ISBN

0-7803-7747-8

Type

conf

DOI

10.1109/PPID.2003.1200913

Filename

1200913