Integrated device and circuit simulation of "dual carrier field effect transistor" and "three dimensional field effect transistor" with effective channel length of 5-20nm and their ASIC and SOC

The concept of "dual carrier field effect transistor" (DCFET) and "three dimensional field effect transistor" (3DFET) and their circuits was established by the authors in 1999. A patent was awarded by the Chinese Patent Office in April 2004. This family of devices and integrated circuits can be fabricated by semiconductor processes compatible with that of CMOS and BJT, yet the effective channel length of these devices can be designed to be 5-20nm, even when fabricated with lithographic techniques for the 90, 65, 45, 32 and 22nm nodes. During 2000-2004, thirteen papers related to the development work of these devices and circuits had been presented as stated in C. Huang et al. (2000). In this paper we present the "integrated device and circuit simulation" of DCFET, 3DFET and their circuits with effective channel length of 5-20nm. An accompanied paper entitled "Device simulation and fabrication of MESA SOI N channel vertical dual carrier field effect transistor with effective channel length of 30 nm for switching ASIC and SOC" by R. Yang et al. for the simulation and fabrication of SOI VDCFET with effective channel length of 30nm is submitted to this conference