DocumentCode
3471354
Title
Leakage Power Reduction for CMOS Combinational Circuits
Author
Zhao, Xiaoying ; Yi, Jiangfang ; Tong, Dong ; Cheng, Xu
Author_Institution
Micro-Processor Res. & Dev. Center, Peking Univ., Beijing
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
1621
Lastpage
1623
Abstract
In this paper, the problem of leakage power reduction by means of input vector control was studied, and a platform for CMOS combinational circuit leakage power reduction was developed. Genetic algorithm is used for searching minimum leakage vector with circuit status difference as fitness function. Experimental results indicate that the method can achieve satisfied leakage power reduction, and the run time is reasonable. This method has no requirement for Spice simulation and independent from target technology
Keywords
CMOS digital integrated circuits; circuit optimisation; combinational circuits; genetic algorithms; CMOS combinational circuits; circuit status difference; fitness function; genetic algorithm; input vector control; leakage power reduction; minimum leakage vector; Biological cells; Circuit simulation; Combinational circuits; Energy consumption; Genetic algorithms; Genetic mutations; Heart; Leakage current; Very large scale integration; Wheels;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306330
Filename
4098491
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