Title :
Leakage Power Reduction for CMOS Combinational Circuits
Author :
Zhao, Xiaoying ; Yi, Jiangfang ; Tong, Dong ; Cheng, Xu
Author_Institution :
Micro-Processor Res. & Dev. Center, Peking Univ., Beijing
Abstract :
In this paper, the problem of leakage power reduction by means of input vector control was studied, and a platform for CMOS combinational circuit leakage power reduction was developed. Genetic algorithm is used for searching minimum leakage vector with circuit status difference as fitness function. Experimental results indicate that the method can achieve satisfied leakage power reduction, and the run time is reasonable. This method has no requirement for Spice simulation and independent from target technology
Keywords :
CMOS digital integrated circuits; circuit optimisation; combinational circuits; genetic algorithms; CMOS combinational circuits; circuit status difference; fitness function; genetic algorithm; input vector control; leakage power reduction; minimum leakage vector; Biological cells; Circuit simulation; Combinational circuits; Energy consumption; Genetic algorithms; Genetic mutations; Heart; Leakage current; Very large scale integration; Wheels;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306330
