Title :
A novel hardware implementation of MP3 decoder for low power and minimum chip size
Author :
Jan-Ti, Yang ; Yu, Jun-Ming
Author_Institution :
Ta Hwa Inst. of Technol., Hsinchu
Abstract :
The structure presented in this paper is for the hardware implementation of MP3 decoder. The purpose is to achieve a controller IC with low power consumption, small chip size and flexible choice of peripheral flash memory. DSP is not required in this design, but a simple 8-bit microcontroller is used instead. The specific hardware circuits can lower the system frequency to save power, and some techniques are applied to reduce the embedded memory
Keywords :
flash memories; low-power electronics; microcontrollers; speech codecs; storage management chips; 8 bit; MP3 decoder; controller IC; embedded memory; low power consumption; microcontroller; peripheral flash memory; small chip size; Circuits; Decoding; Digital audio players; Digital signal processing chips; Energy consumption; Flash memory; Frequency; Hardware; Microcontrollers; Size control;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611513
