Title :
A 2 V 250 MHz multimedia processor
Author :
Yoshida, T. ; Shimazu, Y. ; Yamada, A. ; Holmann, E. ; Nakakimura, K. ; Takata, H. ; Kitao, M. ; Kishi, T. ; Kobayashi, H. ; Sato, M. ; Mohri, A. ; Suzuki, K. ; Ajioka, Y. ; Higashitani, K.
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Abstract :
This paper introduces a VLIW dual-issue RISC processor enhanced with sub-word and DSP instructions for multimedia applications. The processor core integrates 300 k transistors in an 8 mm/sup 2/ area and is implemented with 64 kB RAM onto a 6.0/spl times/6.2 mm/sup 2/ chip in a 2.O V, 0.3 /spl mu/m CMOS process. The processor exploits two modes of parallelism, dual issue instruction execution and 2-way sub-word operation, for a total of four operations per cycle and a peak sustained throughput of 1000 MOPS running at 250 MHz.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; multimedia communication; reduced instruction set computing; video signal processing; 2 V; 250 MHz; CMOS chip; DSP instructions; RAM; VLIW dual-issue RISC processor; multimedia processor; parallelism; two-way sub-word operation; Clocks; Decoding; Games; Multimedia systems; Pipelines; Random access memory; Read-write memory; Reduced instruction set computing; Registers; VLIW;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585382
