Title :
Gate oxide degradation due to plasma damage related charging while ILD cap oxide deposition - detection, localization and resolution
Author :
Schulte, Susanne ; Dubois, Gerard ; Basso, Didier
Author_Institution :
ALTIS Semicond., Corbeil-Essonnes, France
Abstract :
The article reports on the flow of detection, localization and resolution of a plasma damage related problem in a logic chip production line. The problem was observed on standard 0.25 μm logic technology. The introduction and optimization of a voltage breakdown (VBD) test in ILT (in line test) routines led to the detection of an insufficient gate oxide quality. Using data-mining application software and taking into consideration the structure of the test routine, the root cause for the degradation of the gate-oxide was found to be ILD (inter-layer-dielectric) cap oxide deposition. A matrix design of experiment was used to optimize the plasma deposition process in order to minimize charging effects by paying attention to wafer uniformity and reproducibility. It is shown that the principal detractor for the quality of gate oxide was eliminated by introducing the new ILD cap oxide process.
Keywords :
CMOS logic circuits; data mining; design of experiments; dielectric thin films; integrated circuit interconnections; integrated circuit manufacture; integrated circuit reliability; integrated circuit testing; plasma CVD; process monitoring; semiconductor device breakdown; surface charging; 0.25 micron; CMOS technology; ILD cap oxide deposition; data-mining application software; gate oxide degradation; gate oxide quality; inline test; inter-layer-dielectric cap oxide deposition; logic chip production line; matrix design of experiment; plasma damage detection; plasma damage localization; plasma damage related charging; plasma deposition process optimization; test routine structure; voltage breakdown test; wafer reproducibility; wafer uniformity; CMOS technology; Degradation; Dielectric breakdown; Electric breakdown; Logic testing; Optimized production technology; Plasma applications; Plasma measurements; System testing; Voltage;
Conference_Titel :
Plasma- and Process-Induced Damage, 2003 8th International Symposium
Print_ISBN :
0-7803-7747-8
DOI :
10.1109/PPID.2003.1200927
