Gate oxide degradation due to plasma damage related charging while ILD cap oxide deposition - detection, localization and resolution

The article reports on the flow of detection, localization and resolution of a plasma damage related problem in a logic chip production line. The problem was observed on standard 0.25 μm logic technology. The introduction and optimization of a voltage breakdown (VBD) test in ILT (in line test) routines led to the detection of an insufficient gate oxide quality. Using data-mining application software and taking into consideration the structure of the test routine, the root cause for the degradation of the gate-oxide was found to be ILD (inter-layer-dielectric) cap oxide deposition. A matrix design of experiment was used to optimize the plasma deposition process in order to minimize charging effects by paying attention to wafer uniformity and reproducibility. It is shown that the principal detractor for the quality of gate oxide was eliminated by introducing the new ILD cap oxide process.