Title :
23 GOPS programmable systolic array DSP for video signal processing
Author :
Yano, J. ; Miyake, J. ; Urano, M. ; Inoue, G. ; Tsubata, S. ; Ninomiya, K. ; Sokawa, K. ; Miki, Y. ; Onizuka, K. ; Itoh, R. ; Nabatani, H. ; Nishiyama, T. ; Yamaguchi, S.
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
Abstract :
A 23GOPS programmable systolic array DSP for real-time video signal processing, called digital filtering array (DFA), is described. The DFA performs at the 129.6MHz clock rate with its 90 video processing element (VPE) array. HDTV (MUSE) signal decoding can be realized with 3 DFA chips. The DFA also can be used in other video signal processing applications because ofits programmability.
Keywords :
clocks; decoding; digital filters; digital signal processing chips; high definition television; real-time systems; systolic arrays; video signal processing; 129.6 MHz; DSP chips; HDTV; MUSE; clock rate; digital filtering array; programmable systolic array; real-time video signal processing; signal decoding; Clocks; Decoding; Digital filters; Digital signal processing; Digital signal processing chips; Doped fiber amplifiers; Filtering; HDTV; Systolic arrays; Video signal processing;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585383
