DocumentCode :
3471487
Title :
Alternative facility layouts for semiconductor wafer fabrication facilities
Author :
Hase, Rieko ; Uzsoy, Reha ; Takoudis, Christos G.
Author_Institution :
Sch. of Ind. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
1995
fDate :
2-4 Oct 1995
Firstpage :
384
Lastpage :
388
Abstract :
Examines the performance of several different cellular and functional layouts using simulation models of the different facility designs. The performance measure of interest is the mean time in system or cycle time of lots. Our results show that the presence of unreliable machinery causes the performance of cellular layouts to deteriorate, while the presence of significant setup times improves their performance relative to other layouts. The results also indicate that a very modest amount of additional capacity at critical workcenters results in significant improvements in the performance of functional layouts
Keywords :
digital simulation; economics; electronics industry; integrated circuit manufacture; capacity; cellular layouts; cycle time; facility layouts; functional layouts; mean time; semiconductor wafer fabrication facilities; setup times; simulation models; unreliable machinery; Chemical engineering; Electrical equipment industry; Electronics industry; Fabrication; Industrial engineering; Job shop scheduling; Machinery; Manufacturing industries; Manufacturing processes; Production management; Semiconductor device modeling; System performance; Time measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1995. 'Manufacturing Technologies - Present and Future', Seventeenth IEEE/CPMT International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2996-1
Type :
conf
DOI :
10.1109/IEMT.1995.526191
Filename :
526191
Link To Document :
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