Title :
Design of a Low Power Radiation Hardened 256K SRAM
Author :
Haixia, Li ; Weimin, Li ; Jianping, Tan ; Shijin, Lu ; Lei, Chen
Author_Institution :
Beijing Microelectron. Technique Inst.
Abstract :
In this paper a low power radiation hardened 256K SRAM is presented. The dual interlocked storage cell (DICE) and radiation hardened layout techniques have been implemented to achieve radiation hardened. A novel sense amplifier has been proposed and modified self-timing scheme with duplicate cell for low power operation has been adopted in this SRAM. It has consumed only 11% read power dissipation compared with the conventional control circuit, and the access time can decrease 19%
Keywords :
SRAM chips; low-power electronics; radiation hardening (electronics); SRAM; dual interlocked storage cell; low power radiation hardening; modified self-timing scheme; radiation hardened layout techniques; sense amplifier; CMOS logic circuits; Circuit simulation; Decoding; Logic arrays; Logic design; Operational amplifiers; Power dissipation; Radiation hardening; Random access memory; System-on-a-chip;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306360
