High Performance Low-Power Sparse-Tree Binary Adders

Author

Sun, Yan ; Zheng, Dongyu ; Zhang, Minxuan ; Li, Shaoqing

Author_Institution

Sch. of Comput., Nat. Univ. of Defense Technol., Changsha

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1649

Lastpage

1651

Abstract

A new conception called performance-vector is proposed in this paper to measure the performance of prefix adders. According to the theory, a kind of high performance low-power prefix adder with sparse-tree architecture is introduced. The proposed adder is implemented using both static CMOS and semi-dynamic logic. The simulation result shows that this design has higher speed, lower power and smaller power-delay product

Keywords

CMOS logic circuits; adders; trees (mathematics); low-power prefix adder; low-power sparse-tree binary adders; performance vector; power-delay product; semidynamic logic; sparse-tree architecture; static CMOS; Adders; Circuits; Costs; High performance computing; Logic; Performance evaluation; Power dissipation; Routing; Sun; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306361

Filename

4098500

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3471532