Gate-over-driving CMOS architecture for 0.5 V single-power-supply-operated devices

A gate over driving CMOS (GO-CMOS) architecture for 100MHz operation at a 0.5V Vdd has been proposed. GO-CMOS manages power delivery to the transistors as follows: (1) instead of using a Vt of -0.1V or less for all transistors, the power supply voltage is boosted for logic circuitry with a small load capacitance, (2) the gate voltage of the driver transistors is boosted to drive the heavily-loaded output nodes. Power is supplied to the driver transistors directly from the external supply to avoid stressing the embedded charge pump circuit. This architecture is used because the measured leakage current using Vt of -0.1V or less is over 10-times that of a GO-CMOS circuit even considering that the boosting efficiency is only 36%. To verify GO-CMOS, a 96kb SRAM test chip used GO-CMOS circuits.